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Evaluation of Energy-Recovering Interconnects for Low-Power 3D Stacked ICs P. Asimakopoulos1 , G. Van der Plas2 , A. Yakovlev1 and P. Marchal2 1 School of EECE, Newcastle University, UK 2 IMEC, Belgium Abstract—Energy-recovering schemes have been proposed in the literature as an alternative approach to low-power design, while their performance has been demonstrated to be extremely promising when driving large capacitive loads, such as clock distribution networks [1]. This work investigates the
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  Evaluation of Energy-Recovering Interconnects forLow-Power 3D Stacked ICs P. Asimakopoulos 1 , G. Van der Plas 2 , A. Yakovlev 1 and P. Marchal 21 School of EECE, Newcastle University, UK 2 IMEC, Belgium  Abstract —Energy-recovering schemes have been proposed inthe literature as an alternative approach to low-power design,while their performance has been demonstrated to be extremelypromising when driving large capacitive loads, such as clockdistribution networks [1]. This work investigates the potentialof the energy-recovering methodology for improving the energyefficiency of through-silicon via (TSV) interconnects in 3D ICs. I. I NTRODUCTION Energy dissipation is a major concern for battery-poweredmobile systems. In 3D stacked ICs, TSV interconnects enablelow-parasitic direct connections between tiers and can allowfor considerable energy savings when compared to traditionalPCB chip-to-chip interconnections [2]. However, TSV par-asitic capacitance can still become an important source of energy dissipation in large, densely interconnected 3D SoCs,since the combined capacitance and thus the energy requiredto drive TSVs, will increase linearly with the number of tiersand interconnections.Energy-recovering logic has demonstrated great potentialwhen driving large capacitive loads and circuits utilizing thistechnique have been successfully implemented in the past [1],[5]. Energy-recovering designs can break the C  · V  DD energylimit of conventional static CMOS, by spreading out chargetransfer more evenly over an entire switching period andthus making energy dissipation proportional to the operatingfrequency [3]. The result is very low energy dissipation whichcan asymptotically approach zero at low operating frequencies[4].In this paper, an energy-recovering configuration for 3D ICsis presented and an analysis is attempted based on theoreticalmodels. The proposed circuit is evaluated against conventionalstatic CMOS, while the energy efficiency dependence ondesign parameters is extracted.II. P ROPOSED C ONFIGURATION In energy-recovering systems, load capacitances ( C  L ) aretypically driven by resonant sinusoidal waves which chargenodes and recover part of the charge in the falling half-periodof the wave. It can be proven [6] that if a resistive load R ispresent in the current flow path, the energy dissipated on thatload during a full charge/discharge cycle ( 1 f  ) would be: E  DISS = π 2 2( RC  L f  ) C  L V  2 DD (1) If an equivalent capacitive load was driven by conventionalCMOS logic while switching at the same frequency f  , theenergy dissipation per cycle would be: E  CONV  =12 C  L V  2 DD (2) Therefore, as long as the switching frequency is f < 1 π 2 RC L ,energy-recovering designs can save energy when compared toconventional CMOS logic.In a 3D IC, TSVs will provide an interconnection pathfor signals crossing adjacent tiers. Since TSVs can have anappreciable parasitic capacitance [7], which will increase asadditional TSVs are connected in series, ratioed buffer stageswill be required so as to ensure a sharp-rising signal at theoutput of the TSVs. To reduce energy dissipation, an energy-recovering configuration could replace the required bufferingstages allowing only sinusoidal signals crossing TSVs and thussaving energy according to (1).In the proposed 3D interconnecting configuration (Figure1), each tier is clocked with the assistance of conventionalbuffer stages whereas data signals, prior to crossing a TSV,are converted to sinusoidal waves with the use of adiabaticdrivers (Figure 2). Tier1Tier2Tier3 f-f f-f  TSV  ADIABATIC DRIVER  DATAINDATAOUT P2LC  CLKIN CLK BUFFER P2LC  TSV TSVTSV TSVTSV Figure 1. Proposed configuration. The excellent energy efficiency of sinusoidal charging andenergy recovery can considerably reduce energy dissipationfor interconnecting signals. At the same time, compatibilitywith digital logic is retained by converting locally in each tier, 978-1-4244-4512-7/09/$25.00 ©2009 IEEE 978-1-4244-4512-7/09/$25.00 ©2009 IEEE  IN INININOUTOUT Figure 2. Adiabatic driver. the resulting sinusoidal dual-rail pulses back to level signalsthrough Pulse-to-Level converters (P2LC) (Figure 3). VDDININOUT OUT Figure 3. A Pulse-to-Level Converter implementation. III. A NALYSIS Sinusoidal waveforms can be efficiently generated withthe use of a single resonant-tank inductor [8], which whencombined with the adiabatic driver’s resistance ( R TG ) and theTSV capacitance ( C  TSV  ), forms an RLC oscillator (Figure 4)resonating at: f  =12 π √ L ind C  TSV  (3) VDD/2AdiabaticDriver LC TSV R ind M1R TGATE T=1/f  Figure 4. Resonant pulse generator. The bulk of the energy dissipation in the proposed configu-ration will occur on the adiabatic driver, the inductor’s parasiticresistance ( R ind ) and transistor M1. Since the sinusoidal pulseswill have to be converted back to level-signals after crossinga TSV, the P2L converters will contribute to the total energydissipation as well.  A. Adiabatic driver  The adiabatic driver used in this configuration (Figure 2)is based on adiabatic circuits presented in [9], [10], with theload capacitance replaced by the parasitic capacitance of TSVs( C  TSV  ).Energy in the adiabatic driver is dissipated both on thetransmission-gate resistance ( R TG ) and for driving its inputcapacitance. Assuming that both nFET and pFET transistorsare equally sized ( W  n ), the cross-coupled pFETs reduce theconventionally-driven input capacitance by ½, however theirgate capacitance ( C  n ) will appear as an additional capacitiveload to the driver. Furthermore, drain/source diffusion capac-itance ( C  D ) can be an important portion of the load since ineach cycle 6 C  D will be present in the current flow path (4contributed by the ON T-gate and 2 by the OFF T-gate).Therefore the combined load capacitance will be: C  L = C  TSV  + C  n + 6 C  D (4) The resistance of the T-gate ( R TG ) can be related to the gatecapacitance by a “Device technology factor” ( κ TG ) [11], whichwe can define for our convenience: κ TG = R TG C  n → R TG = κ TG C  n (5) Combining (1), (4) and (5) gives the total dissipated energyper cycle in the adiabatic driver: E  AD = C  n V  2 DD + π 2 2 κ TG C  n f  [ C  TSV  + C  n + 6 C  D ] 2 V  2 DD (6) The second term of (6) has a consistent contribution tothe energy dissipation on every cycle, while the first term isdependent on the data switching activity ( D ) .We can also further simplify this equation by defining thediffusion capacitance as a fraction of the input capacitance, C  D = bC  n (7) and equating term π 2 2 κ TG f  to a variable, y = π 2 2 κ TG f  (8) Equation (6) then becomes: E  AD = D · C  n V  2 DD + yC  n [ C  TSV  + (6 b + 1) C  n ] 2 V  2 DD = » C  n „ Dy + (6 b + 1) 2 « +1 C  n C  2 TSV  – · yV  2 DD +(12 b + 2) C  TSV  · yV  2 DD (9) Since in (9) C  n is the free parameter, the first two termsof (9) are inversely proportional and E  AD is minimized whenthey become equal. The value of the gate capacitance at thatpoint is calculated as: C  n ( opt ) = s  [ Dy + (6 b + 1) 2 ] − 1 C  TSV  (10) Combining (9) and (10) results in minimum energy dissi-pation for the adiabatic driver, which is: E  AD ( min ) = s  Dy + (6 b + 1) 2 + (6 b + 1) # · 2 yC  TSV  V  2 DD (11) Replacing variable y in (11), we can observe the dependenceof the energy dissipation on parameters f  and κ TG : E  AD = s  2 Dπ 2 κ TG f  + (6 b + 1) 2 + (6 b + 1) # · π 2 κ TG fC  TSV  V  2 DD (12)   B. Switch M1 Respectively, the energy dissipation on M1 which isswitched-on briefly to recover the energy dissipated each cycleon the R total = R TG + R ind , is a trade-off between dissipationon its on-resistance R M  1 and input capacitance C  M  1 . Since M1is a fairly large transistor, previous ratioed stages will have asignificant energy consumption. For that reason a m factor isused to compensate for the additional losses. I  M  1( rms ) is therms current passing through the transistor while turned-on and V  GM  1 is the peak gate voltage. A methodology for derivingoptimum values for both these parameters is proposed in [8].The total dissipated energy on M1 can be calculated as: E  M  1 = mC  M  1 V  2 GM  1 + I  2 M  1( rms ) R M  1 f  (13) For transistor M1 we can also define a “Device technologyfactor”: κ M  1 = R M  1 C  M  1 ⇒ R M  1 = κ M  1 C  M  1 (14) Substituting R M  1 into (13): E  M  1 = mC  M  1 V  2 GM  1 +1 C  M  1 I  2 M  1( rms ) κ M  1 f  (15) Minimum energy consumption will occur when the twoterms of (15) are equal: C  M  1( opt ) = r  κ M  1 mf I  M  1( rms ) V  GM  1 (16) E  M  1( min ) = 2 I  M  1( rms ) V  GM  1 r  mκ M  1 f  (17) C. Inductor’s parasitic resistance The inductor’s ( L ind ) parasitic resistance R ind is propor-tional to the Q ind factor, which is typically implementationtechnology dependent. For the purposes of this analysis it canbe estimated as: Q ind =1 R ind s  L ind C  L ⇒ R ind =1 Q ind s  L ind C  L ⇒ R ind =1 Q ind C  L 2 πf  (18) Energy dissipation on R ind can be estimated using (1) as: E  ind = π 2 2( R ind C  L f  ) C  L V  2 DD (19) Combining (18) and (19) we calculate the inductor’s energydependence on the Q ind factor: E  ind = π 4 C  L Q ind V  2 DD (20)  D. Total energy dissipation The total dissipated energy for the adiabatic driver, switchM1 and inductor’s resistance can be calculated by combining(12), (17) and (20): E  total = E  AD + E  M  1 + E  ind (21) Nevertheless, for (21) to be complete the energy contri-bution of the P2L converters has to be included as well,which cannot be theoretically derived and is addressed in thefollowing sections.IV. E VALUATION For the evaluation of the proposed method, the κ TG , κ M  1 and C  D parameters were extracted using simulation modelsfor a 130nm process. The TSV capacitance was assumed to be160fF, a value which can be either derived from a single TSVor a series combination of TSVs distributed among subsequenttiers in a 3D IC. The supply voltage was at 1.2V and dataswitching activity was assumed to be equal to 1.All parameters were inserted into (21) and the energydissipation per bit per cycle was calculated, with the operatingfrequency and Q factor as free variables. An identical circuitconfiguration was simulated as well in a commercial SPICEprogram and the simulation data showed good correlation withthe theoretical estimations.The inductor’s quality factor can have a considerable effecton the energy dissipation and this can be observed in Figure 5,where the estimated energy dissipation is plotted for variousoperating frequencies. 579111315171920406080100120   500Mhz300Mhz100Mhz Q factor     E  n  e  r  g  y   (   f   J   ) Figure 5. Estimated energy dissipation at 500, 200, 100 MHz. TSV=160fF. V. C OMPARISON The proposed configuration was compared to a conventionalCMOS buffer with ratioed stages driving an equivalent TSVload capacitance. Since the conventional buffer when trans-mitting data will produce just one charging event per 2 cyclesof the operating frequency, its energy dissipation per cycleis calculated as in (2). If we also include the data switchingactivity, then: E  CONV  = D · 12 C  L V  2 DD (22) The estimated energy performance improvement of theproposed configuration over the conventional buffer for D = 1 ,can be seen in Figure 6.    579111315171901020304050607080   500Mhz300Mhz100Mhz Q factor     I  m  p  r  o  v  e  m  e  n   t   (   %   ) Figure 6. Energy performance improvement of the proposed energy-recovering configuration over a conventional buffer driving an equivalent TSVload capacitance.   57911131517190102030405060   80fF120fF160fF Q factor     I  m  p  r  o  v  e  m  e  n   t   (   %   ) Figure 7. Energy dissipation reduction at 300MHz when P2LC is includedand the TSV load is variable. Varying the value of the TSV load capacitance has noeffect on the estimated energy improvement percentage, asthe energy dissipation for both the proposed method and theconventional buffer is linearly related to the load capacitance.However, the data plotted in Figures 5, 6 can be consideredas the theoretical maximum performance attainable by theenergy-recovering method, since the energy dissipation of theP2L converters is not included in these estimations.To include the effect of the P2L converters in the energycalculations, a simple circuit topology is chosen (Figure 3) andits energy dissipation is extracted from simulation data. Sincethe P2L converter has constant energy dissipation regardlessof the value of the TSV capacitance, the linear relation of the total dissipated energy to the load capacitance value isno longer valid for the energy-recovering circuit. This can beobserved in Figure 7, where the estimated energy improvementis plotted at 300MHz operating frequency and the TSV loadcapacitance is variable. It can be expected that as the loadcapacitance increases, energy performance would approach theestimations in Figure 6.Switching activity can also be a significant factor affectingenergy performance. Since in the energy-recovering circuitthe sinewave oscillation cannot be halted, all capacitancesin the current flow path will charge and discharge on eachcycle regardless of data activity. In contrast, static CMOSideally dissipates energy only when switching and thus theenergy-recovering circuit can compare favorably only at highswitching rates. In Figure 8, the estimated effect of theswitching activity on energy performance is plotted for an   5791113151719-40-30-20-100102030405060   0.60.81 Q factor     I  m  p  r  o  v  e  m  e  n   t   (   %   ) Figure 8. Improvement in energy dissipation when P2LC is included andswitching activity is variable. f=300MHz, TSV=160fF.   5791113151719010203040506070   130nm65nm Q factor     I  m  p  r  o  v  e  m  e  n   t   (   %   ) Figure 9. Improvement in energy dissipation when P2LC is included andprocess technology is variable. f=300MHz, TSV=160fF. operating frequency of 300Mhz.Since the technology factors κ TG and κ M  1 were extractedfor the 130nm process, reducing their value by ½ couldalso provide us with an estimation of the circuit’s energyperformance for the 65nm node. The result in plotted inFigure 9 and as can be observed, technology scaling has apositive effect on energy dissipation when compared to theconventional buffer.VI. C ONCLUSIONS In this work, a theoretical analysis was developed to in-vestigate the potential of the energy-recovering methodology,as used in adiabatic logic and resonant clock distributionnetworks, for reducing the energy dissipation of 3D IC inter-connects. The total energy dissipation per cycle and optimumdevice sizing were extracted for the proposed method using thetheoretical models. Simulation data showed good correlationwith the theoretical estimations on a 130nm process.The proposed configuration was compared against a con-ventional CMOS buffer, driving an equivalent TSV load ca-pacitance and its energy performance was evaluated. Analysisrevealed energy dependence on Q , f  , D and TSV capacitanceparameters and the results demonstrated favorable energyperformance for high Q factors/switching activities/TSV ca-pacitances and low operating frequencies. Furthermore, anestimation was provided on the energy performance behaviorof the energy-recovering design in an advanced technologynode, where improved efficiency was demonstrated.
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