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Abstract—This paper presents a novel sinusoidal pulsewidth
modulation control method with voltage balancing capability for
the diode-clamped five-level rectifier/inverter system. A complete
analysis of the voltage balance theory is given. The voltage balancing effects of the third harmonic offset injection to all three-phase
voltages are discussed. The proposed control utilizes the offset
voltage to regulate the average currents flowing into and out of the
inner junction without affecting output line-to-line voltage. The
voltage balancing was achieved by selecting proper offset voltages
for both sides. A five-level experimental system is built up and used
to prove the theory.

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1028 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 45, NO. 3, MAY/JUNE 2009
A Sinusoidal PWM Method With Voltage BalancingCapability for Diode-Clamped Five-Level Converters
Zhiguo Pan,
Member, IEEE
, and Fang Zheng Peng,
Fellow, IEEE
Abstract
—This paper presents a novel sinusoidal pulsewidthmodulation control method with voltage balancing capability forthe diode-clamped ﬁve-level rectiﬁer/inverter system. A completeanalysis of the voltage balance theory is given. The voltage balanc-ing effects of the third harmonic offset injection to all three-phasevoltages are discussed. The proposed control utilizes the offsetvoltage to regulate the average currents ﬂowing into and out of theinner junction without affecting output line-to-line voltage. Thevoltage balancing was achieved by selecting proper offset voltagesfor both sides. A ﬁve-level experimental system is built up and usedto prove the theory.
Index Terms
—AC motor drive, active rectiﬁer, multilevelconverter.
I. I
NTRODUCTION
I
N RECENT YEARS, multilevel converters have begun toplay a more and more important role in medium-voltagehigh-power applications. Compared with traditional two-levelvoltage converters, the primary advantages of multilevel con-verters are their smaller output voltage steps, which resultin higher power quality, lower harmonic components, highervoltage capability, better electromagnetic compatibility, andlower switching losses [1], [2].The multilevel converter synthesizes the staircase outputvoltage which follows the sinusoidal waveform with minimumharmonics. In order to satisfy the same harmonic requirement,the frequency needed by the multilevel converter is much lowerthan the conventional converter. Therefore, the multilevel con-verter can achieve higher efﬁciency. The multilevel convertersalso have lower
dV/dt
[3], [4]. It has been found recentlythat the high
dV/dt
in the high-power pulsewidth modulation(PWM) converter can induce corona discharge and lead tobearing or winding insulation failure.The multiple dc-bus capacitors in multilevel converters pro-vide the capability of outputting multilevel voltage waveform.
Paper IPCSD-08-080, presented at the 2007 IEEE Applied Power Elec-tronics Conference and Exposition, Anaheim, CA, February 25–March 1,and approved for publication in the IEEE T
RANSACTIONS ON
I
NDUSTRY
A
PPLICATIONS
by the Industrial Power Converter Committee of the IEEEIndustry Applications Society. Manuscript submitted for review June 26, 2007and released for publication November 17, 2008. Current version publishedMay 20, 2009.Z. Pan is with the ABB Corporate Research Center, Raleigh, NC 27606-5200USA (e-mail: z.pan@ieee.org).F. Z. Peng is with the Department of Electrical Engineering, Michigan StateUniversity, East Lansing, MI 48824 USA (e-mail: fzpeng@egr.msu.edu).Color versions of one or more of the ﬁgures in this paper are available onlineat http://ieeexplore.ieee.org.Digital Object Identiﬁer 10.1109/TIA.2009.2018962
However, it also requires additional circuits and special controlmethods to keep the capacitor voltages well balanced. For thethree-level diode-clamped converter, because there are only oneadditional voltage junction, the neutral point, and the symmetryof the upper and lower capacitors, it has self-voltage balancingpotential. However, the neutral point has a low frequency rippleat three times of the fundamental frequency. Some new researchworks have addressed on eliminating or attenuating the lowfrequency ripple [5]–[8].However, the dc-bus voltage balancing for diode-clampedmultilevel converters with the number of levels greater thanthree is more complicated. The multilevel converter capacitorstend to overcharge or completely discharge. Eventually, theconverter converges to a three-level converter. Corzine
et al.
proposed a dc–dc front end to regulate the center capacitorvoltage of a four-level converter [9]. PWM hysteresis controlmethod has been proposed to regulate the dc bus of a ﬁve-level rectiﬁer [10]. Then, the multiband hysteresis comparatorcontrol strategy has been extended to a ﬁve-level back-to-back system. Although the technique is simple, the characteristicsare not sufﬁcient as a motor drive system. Thus, an improvedcontrol strategy using the space vector PWM has also beenproposed. The improved control strategy is able to solve thevoltage ripples in the dc link [11], [12]. Similar voltage balanc-ing technique has also been discussed in [13]–[15].A voltage balancing control method for the ﬁve-level back-to-back rectiﬁer/inverter system is presented in [16] and [17].The method relies on coordination between the rectiﬁer andinverter switching angles to achieve capacitor charge balanceand, at the same time, minimize the switching harmonics of both the rectiﬁer and inverter. Although the voltage balancingcan be achieved in all operation ranges, the output voltage stillhas lower order harmonic components due to limited switchingper cycle. This problem will get more prominent when the mod-ulation index is low due to fundamental frequency switchingand the constraint of the charge balancing.In thispaper, the voltage balancing control theory isextendedto sinusoidal PWM (SPWM), which is simple, easy to beimplemented, and able to effectively reduce the lower orderharmonic components. A per-unit approach is used to analyzethe average current ﬂowing into or out of the inner junction.The voltage balancing effects of the third harmonic voltageinjection added to all three-phase voltages are discussed andutilized to balance the dc bus voltage. By selecting proper offsetvoltages on both rectiﬁer and inverter sides, the average currentﬂowing into the inner junction can be adjusted to be equal tothat ﬂowing out from it, therefore balancing the dc-bus voltage.Meanwhile, the output voltage remains the same because of the
0093-9994/$25.00 © 2009 IEEE
PAN AND PENG: PWM METHOD WITH VOLTAGE BALANCING CAPABILITY FOR DIODE-CLAMPED CONVERTERS 1029
Fig.1. Simpliﬁedﬁve-leveldiode-clampedback-to-backconverter(onephaseleg only).
line-to-line voltage redundancy. Simulation results are providedto prove the voltage balancing capability of the proposed con-trol. A ﬁve-level experimental system is built up and used tovalidate the theory.II. V
OLTAGE
B
ALANCING OF
F
UNDAMENTAL
F
REQUENCY
S
WITCHING
Fig. 1 shows a simpliﬁed ﬁve-level diode-clamped back-to-back converter, where only one phase leg is considered becauseof the symmetry. In the back-to-back structure, two identicalﬁve-level converters are connected with a shared dc bus. Theleft half side is connected to the utility and acts as a rectiﬁer,while the right half side is connected to the load and actsas an inverter. Although the back-to-back topology requiresdoubling the number of switching devices, it has the followingadvantages:1) lower input current harmonics;2) bidirectional power ﬂow control;3) ability to control the voltage of the dc bus;4) ability to control an input power factor.For the multilevel converter, the back-to-back topologycan also regulate the voltage of each dc bus. Because of thesymmetry of the system, the unbalance tendencies of both sideshaveapotentialtocompensateeachother.Withapropercontrolstrategy, net current ﬂowing into each level can be regulatedto zero.Since the reactive components of the current for both therectiﬁer and inverter have no effect on the voltage balance, onlythe active components of the currents need to be considered[16]. The voltage and the active current waveforms for aﬁve-level back-to-back system are shown in Fig. 2. Fig. 2(a)shows the voltage and current waveforms of the rectiﬁer, where
V
R
and
V
R
1
are the rectiﬁer staircase voltage waveform andits fundamental component, respectively, and
i
R
is the activerectiﬁer current waveform. Fig. 2(b) shows the waveforms of the inverter.Because of the symmetry, we only need to balance the inner junction
V
4
. In order to balance junction
V
4
, the average net
Fig. 2. Voltage and current waveforms of the rectiﬁer and inverter side.Fig. 3. Five-level SPWM output voltage and inner junction current.
charge ﬂowing into the junction
V
4
should be zero, i.e.,
θ
R
2
θ
R
1
i
R
sin
θdθ
=
θ
I
2
θ
I
1
i
L
sin
θdθ.
(1)Then, we can get the charge balancing equation
I
R
(cos
θ
R
2
−
cos
θ
R
1
) =
I
L
(cos
θ
I
2
−
cos
θ
I
1
)
(2)where
I
R
and
I
L
are the amplitude of the rectiﬁer currentand the load current, respectively. Combined with other systemconstraints, the switching angle combinations that satisfy thevoltage balance requirement can be calculated, and the one withlowest total harmonic distortion (THD) is chosen [16].III. C
ARRIER
-B
ASED
SPWM C
ONTROL
The carrier-based SPWM control is proven to be able toeffectively reduce the lower harmonic components. Fig. 3(a)shows the ﬁve-level SPWM voltage waveform, where the mod-ulation index
M
is 0.85. The sinusoidal reference voltage
v
ref
is given by
v
ref
=
M
·
V
dc
2 sin
θ.
(3)
1030 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 45, NO. 3, MAY/JUNE 2009
Unlike the traditional two-level converter, which only has onetriangular carrier, the ﬁve-level converter has four triangularcarriers, each one representing one capacitor in the dc bus.In order to investigate the average current ﬂowing into theinner junction, similar method from the fundamental frequencyswitching can be used. Assuming that the current is sinusoidaland in phase with the voltage, we can generate the currentﬂowing into or out of the inner junction
V
4
according to thevoltage waveform, as shown in Fig. 3(b). Since the SPWMcontrol is used, the current ﬂowing into
V
4
has more pulses.The average inner junction current
I
avg
, which is deﬁned as theaverage current ﬂowing into/out of the inner junction
V
4
, can becalculated based on the current waveform by
I
avg∆
=
2
π
0
i
2
π
=
I
pk
2
π
·
i
(cos
θ
si
−
cos
θ
ei
)
(4)where
θ
s
and
θ
e
are the start and end angles of each pulse,which are determined by the voltage reference
V
ref
and thetriangular carrier, and
I
pk
is the peak value of the current.The peak current
I
pk
is determined by the input/output powerand rectiﬁer/inverter voltage, as shown in
I
pk
=
√
2
P
3
V
R
=
√
2
P
3
·
M
·
V
dc
2
√
2
.
(5)Substitute (5) into (4), we can get
I
avg
= 4
P
3
V
dc
·
i
(cos
θ
si
−
cos
θ
ei
)
πM .
(6)To simplify the analysis, the average inner junction currentcan be normalized by choosing the base value as
I
avg
,
base
= 4
P
3
V
dc
.
(7)Accordingly, the per-unit value of the average inner junctioncurrent
I
avg
is given as
I
avg
=
i
(cos
θ
si
−
cos
θ
ei
)
πM .
(8)Since the voltage of the inner junction is based on thenet current ﬂowing into the junction, in order to balance the junction voltage, the average inner junction current ﬂowing into
V
4
in the rectiﬁer side
I
avg
,
in
must be equal to the averageinner junction current ﬂowing out of
V
4
in the inverter side
I
avg
,
out
. In the per-unit systems, the base value is determinedby the system operation point only, and the per-unit value isdetermined by the control method, modulation indexes, andswitching angels. Since the
I
avg
,
base
values for both sides arethe same, we only need to compare the per-unit values
I
avg
for both sides. Once the control strategy is determined,
I
avg
can be calculated without the actual voltage and current. Theusage of the per-unit value makes the analysis more simple anduniversal.Similarly, the per-unit value can be used for the referencevoltage
V
ref
and the current
i
L
,
i
4
. The base value of thevoltage chosen is the voltage of each dc-bus capacitor, which
Fig. 4. Inner junction current for a given reference voltage. (a) Referencevoltage. (b) Duty cycle of inner junction current
i
4
. (c) Equivalent
i
4
.
is
V
dc
/
4
, and the base value of the current is
I
pk
. Therefore,we have
V
ref
=
v
ref
V
dc
/
4 = 2
M
(9)
i
L
=
i
L
/I
pk
= sin
θ
(10)
i
4
=
i
4
/I
pk
.
(11)Accordingly, the voltages of the ﬁve dc-bus junctions become
±
2,
±
1, and 0.The switching angles in (8) are determined not only by themodulation index but also by carrier frequency factor and thephase angles of each carrier. Therefore, it is complicated tocalculate all the switching angles, particularly when the carrierfrequency factor
m
f
is high. On the other hand, it can beseen from Fig. 3(b) that the envelope of the current waveformfollows the sinusoidal reference. The current waveform can beapproximated to a series of current pulses whose duty cycleis determined by the voltage reference. Therefore, when thecarrier frequency is far greater than the fundamental frequency,the sinusoidal reference can be assumed as a constant valueduring each switching cycle. Thus, the duty cycle of the PWMwaveform can be calculated, and the duty cycle of the currentﬂowing into junction
V
4
can be written as
D
i
4
=
2
−
v
ref
,
if
1
≤
v
ref
≤
2
v
ref
,
if
0
≤
v
ref
≤
1
.
(12)It can be further simpliﬁed to
D
i
4
(
θ
)=
1
−
abs
(1
−
abs
(2
M
sin
θ
))
,
when
θ
≤
π
0
,
when
θ > π.
(13)Therefore,
i
4
can be approximated as the duty cycle timesthe load current. Since the per-unit value of load current is asinusoidal waveform with a peak value of one, the equivalent
i
4
can be deﬁned as
i
4eq
(
θ
) =
D
i
4
(
θ
)
·
sin
θ.
(14)Fig. 4 shows the approximate waveform of the duty cycle of current
i
4
, where
M
equals 0.9. From Fig. 4(b), it can be seen
PAN AND PENG: PWM METHOD WITH VOLTAGE BALANCING CAPABILITY FOR DIODE-CLAMPED CONVERTERS 1031
Fig. 5. Average inner junction currents versus
M
and
m
f
for SPWM control.
that
D
i
4
is higher when
v
ref
is close to one, and it is lowerwhen
v
ref
is close to zero or two. Fig. 4(c) shows the equivalentcurrent
i
4eq
ﬂowing into/out of junction
V
4
. The average inner junction current in per-unit value can be obtained by
I
avg
= 1
πM
2
π
0
i
4
dθ
≈
1
πM
2
π
0
D
i
4
i
L
dθ
= 1
πM
2
π
0
D
i
4
·
sin
θdθ
= 1
πM
π
0
1
−
abs
(1
−
abs(2
M
sin
θ
))
·
sin
θdθ.
(15)For
M
= 0
.
9
,
I
avg
can be calculated by (15) as 0.3496. Fig. 5shows the average inner junction current of the SPWM controlfor different modulation indexes and different carrier frequencyfactors. The solid line shows the results of the simpliﬁcationwhen the carrier frequency factor is high. The stars show theaverage current for different modulation indexes when
m
f
= 7
,and the dots show the results when
m
f
= 15
. It can be seen thatthe results from the simpliﬁed method are close to the resultsfrom the one using actual switching angles, particularly when
m
f
is greater than 15. Since
m
f
is usually greater than 15, theaverage inner junction current can be calculated without
m
f
,which makes it easier to analyze the charge balancing.However, based on the analysis before, the average inputcurrent
I
avg
,
in
has to equal the average output current
I
avg
,
out
to keep the voltage balanced. Unfortunately, it can only beguaranteed when both
M
R
and
M
I
are less than 0.5, whichmeans that the ﬁve-level converter has degraded to a three-levelconverter, or
M
R
equals
M
I
, which limits the capability toperform variable frequency drive.IV. R
EGULATION OF THE
A
VERAGE
I
NNER
J
UNCTION
C
URRENT
For the SPWM control, the average current is determinedby the output voltage reference. Unlike the switch-angle-based
Fig. 6. Offset voltage with minimum inner junction current.
control algorithm discussed in [16] and [17], the switch anglescannot be directly controlled in SPWM control. Instead, theoutput voltage reference has to be changed to regulate theaverage inner junction current.Fortunately, the line-to-line redundancy of three-phase sys-tem provides the possibility to change the phase voltage whilekeeping the output line-to-line voltage the same. By addingproper offset voltage to all three-phase voltages, it is possibleto regulate the average current ﬂowing into junction
V
4
withoutchanging the output line-to-line voltage.Theoutputcurrentisconstantintheper-unitsystem,whichisa unit sinusoidal waveform. If we want to reduce average inner junction current
I
avg
, we need to reduce the duty cycle
D
i
4
,which means choosing an offset voltage that makes
v
ref
closerto zero or two. On the contrary, if we want to increase
I
avg
, weneed to choose an offset voltage that makes
v
ref
closer to one.In order to keep the symmetry between the three-phasevoltages and within each phase voltage, the frequency of offsetvoltage needs to be three times the fundamental frequency.Therefore, for each
2
π
cycle waveform of
v
oﬀset
, only
π/
6
can be changed independently. Since the average inner junctioncurrent is proportional to the integration of the production of the duty cycle
D
and
sin
θ
, as shown in (15), the duty cycle
D
has more inﬂuences on
I
avg
when
sin
θ
has a higher value.Therefore, the offset voltage
v
oﬀset
will be chosen based on itseffect at
[
π/
3
,π/
2]
, where
i
L
reaches its peak.Take the waveforms shown in Fig. 4 as an example. In orderto minimized the average inner junction current, the offsetvoltage needs to be chosen so that the phase voltage referenceis close to zero or two. Based on that, an offset voltage isdetermined and is shown in Fig. 6(a) and (b) with the sinusoidalreference voltage, and the phase voltage reference after theoffset voltage is added. The equivalent inner junction current
i
4eq
can be calculated by (14) and shown in Fig. 6(c). It can beseen that the new phase voltage is equal to two when
θ
is in
[
π/
3
,
2
π/
3]
; therefore, the inner junction current in that rangebecomes zero. Therefore, the average inner junction current of this control method reduced from 0.35 to 0.27.Similarly, we can choose an offset voltage to maximize theaverage current by making the phase voltage close to one.

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