Modeling and Simulation Lab

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Modeling and Simulation Lab Manual for Final Year ECE Under Anna University of Technology, Coimbatore
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  Department of ECEModeling and Simulation Lab Record MODELING AND SIMULATION LABSYLLABUS LIST OF EXPERIMENTS: 1. FPGA Implementation of Simple Alarm System2.FPGA Implementation of Parity Checker3.FPGA Implementation of Scrolling Display 4. FPGA Implementation of Multimode Calculator5.FPGA Implementation of Multimode Calculators6.Modeling and Prototyping with Simulink and Code Composer Studiowith DSK 7.Graphical Simulation and Modeling using MATLAB8.Simulation of Delta Modulation, Adaptive Delta Modulation and QPSK Constellation 1Vidyaa Vikas College of Engineering and Technology  Department of ECEModeling and Simulation Lab Record Exp.No: ________Date: __________________ 2Vidyaa Vikas College of Engineering and Technology  Department of ECEModeling and Simulation Lab Record 1. A) FPGA IMPLEMENTATION OF SIMPLE ALARMSYSTEMAIM:  To design and implement Simple Alarm System using FPGA TOOLS REQUIRED: Simulation:   ModelSimSynthesis : Xilinx 9.2i SIMULATION PROCEDURE: 1.To start the programs click the modelsim software. 2.  The main page is opened, click the file option to create a new sourcein VHDL.3.After the program is typed, it is saved in a name with extension’ .vhd’4.Then the program is compiled and errors are checked.5.After that it is simulated.6.Then the program is viewed and the signal option is clicked from theview menu and input signals are given.7.Then in the edit option, force is selected and the values are given.8.Finally Add – wave is clicked view the result waveform. SYNTHESIS PROCEDURE: 1. In the Xilinx, open a new project and give the file name.2.Select VHDL module from XC3S400-4pq208.3.Type the program and create new source.4.Select implementation constraint file and give the file name. 5.  Then click assign package pin (run) from user constraints.6.Give the pin location and save the file. 7. Run the synthesis XST, implement design and generate program filesequentially.8.Select program and wait until it gets succeed.9.Give the input and observe the output in the Xilinx kit. 3Vidyaa Vikas College of Engineering and Technology  Department of ECEModeling and Simulation Lab Record PROGRAM: library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity alarm isPORT (clk, rst, remote, sensors: IN STD_LOGIC;siren: OUT STD_LOGIC);end alarm;architecture Behavioral of alarm is TYPE alarm_state is (disarmed, armed, intrusion);ATTRIBUTE enum_encoding: STRING;ATTRIBUTE enum_encoding OF alarm_state: TYPE IS sequential ;SIGNAL pr_state, nx_state: alarm_state;SIGNAL flag: STD_LOGIC;begin----- Flag: -----------------------------PROCESS (remote, rst)BEGINIF (rst='1') THENflag <= '0';ELSIF (remote'EVENT AND remote='0') THENflag <= NOT flag;END IF;END PROCESS;----- Lower section: --------------------PROCESS (clk, rst)BEGINIF (rst='1') THENpr_state <= disarmed;ELSIF (clk'EVENT AND clk='1') THEN 4Vidyaa Vikas College of Engineering and Technology
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